|
課程名稱 |
高階合成技術於應用加速專題
Special Project on Application Acceleration with High-Level-Synthesis |
|
開課學期 |
110-2 |
|
授課對象 |
電機資訊學院 電子工程學研究所 |
|
授課教師 |
賴 瑾 |
|
課號 |
EEE5062 |
|
課程識別碼 |
943 U0640 |
|
班次 |
|
|
學分 |
1.0 |
|
全/半年 |
半年 |
|
必/選修 |
選修 |
|
上課時間 |
星期四7,8,9(14:20~17:20) |
|
上課地點 |
電二101 |
|
備註 |
總人數上限：20人 |
|
|
|
|
課程簡介影片 |
|
|
核心能力關聯 |
核心能力與課程規劃關聯圖 |
|
課程大綱
|
|
為確保您我的權利,請尊重智慧財產權及不得非法影印
|
|
課程概述 |
This special project course is offered for students who want to continue advanced study on High-Level-Synthesis (HLS). It includes but is not limited to the following:
1. Enhance the functionality, performance of the final project from the course "Application Acceleration with High-Level Synthesis"
2. Apply HLS on thesis research
3. Application area that links with industry.
4. You may choose to work on the following projects. There are some baselined codes/framework available for reference.
- "AIoT – Apply accelerated signal processing and neural network in a composable pipeline framework."
- "Accelerated Algorithmic Trading" - A platform based on Xilinx AAT
- "Advanced Processor Architecture using HLS RISC-V" - A based-line HLS-RISCV for reference
- "Neuron Network Accelerator" - based on FINN framework
- "Implement a huge Matrix-Matrix-Multiplication Problem with HLS"
- Develop course lab for the following subjects - Research Assistant Scholarship offered
- Embedded System and Logic Design
- Digital Signal Processing
- Image Processing
- Computer Architecture
- Neuron Network Architecture
- Algorithm
- Numerical Analysis 待補 |
|
課程目標 |
1. Develop system-level analysis and implementation capabilities
2. Develop end-to-end application acceleration for an application area待補 |
|
課程要求 |
1. Course: "Application Acceleration with High-Level Synthesis"
2. Experience in using HLS to develop kernel function or application acceleration.待補 |
|
預期每週課後學習時數 |
|
|
Office Hours |
另約時間 備註： There is an official discussion session on Thursday 7,8,9(14:20~17:20). Individual discussion session may be arranged based on project need. |
|
指定閱讀 |
TBD based on project content. |
|
參考書目 |
• HLS Textbook, www.boledu.org
• Xilinx ug902: Vivado Design Suite User Guide: High-Level Synthesis,
https://bit.ly/3x4r8mp
• Xilinx ug1399 Vitis High-Level Synthesis User Guide:
https://docs.xilinx.com/r/en-US/ug1399-vitis-hls
|
|
評量方式
(僅供參考) |
|
|
週次 |
日期 |
單元主題 |
|
第4週 |
3/10 |
Complete Problem definition and exploration
Deliverables:
o A preliminary target project specification is defined.
o Identify a reference design to work. |
|
第8週 |
4/07 |
System analysis and findings
Performed preliminary analysis on the reference design, by
1. Duplicate the implementation from an academic paper
2. Rebuild and duplicate the open-sourced design
3. Analyze performance, power, area, or other metrics to measure the quality of the project
Deliverables:
o Build up the target system
o Identify the area to work on,
o Define a more accurate target specification, and its measurement method
o Define the verification scheme |
|
第14週 |
5/19 |
System implementation and optimization
Perform system level implementation. It includes host application and kernel acceleration.
The candidate may adjust the direction of work content based on new findings.
Deliverables:
o A running system that passes verification suite
o The system meets the target specification |
|
第18週 |
6/16 |
Report and Presentation/Teaching
The candidate shall document the research result in detail to enable other people to learn the technology quickly. In addition, the candidate is encouraged to give a teaching session.
Deliverables
o Document/Report and presentation material
o Teaching sessions |
|